Substrate Zero
Yield simulation for analog AI (memristor-based neuromorphic) chips
A complete prototype, validated in the lab on stated parameters.
Towards zero spread. Not zero defects.
- The problem
- Manufacturing defects are unavoidable. On dense analog chips, one bad component can spread and take the whole array down. Designers usually learn where that breaking point sits after the chip is built.
- What exists
- A working simulation engine, an API and a dashboard, tested end to end. For a given design, it finds the defect rate at which fault tolerance breaks down, based on the device assumptions the designer provides.
- What it is not yet
- A target-matching model. It has not been calibrated against measured wafer data, and no outside team has run it. Its answer is only as good as the assumptions put in.
- Built to stay blind
- It accepts physical parameters only. Names, company details and project titles are rejected before any simulation runs.
- What moves it to TRL 5
- Measured defect or yield data from a research lab, used to calibrate the model and check it against real results.
- The goal
- Seeking a research group with measured defect or yield data. In return: a year of free access and co-authorship credit on published validation work.
Substrate Zero is part of the ET-ERNITY group of companies.